Semiconductor device and method of fabricating the same

ABSTRACT

An impurity having a conductivity type same as that contained in a source-and-drain region is implanted to an exposed surface of a gate electrode along a direction inclined to the surface of said semiconductor substrate, while using over-etched sidewalls as a mask, where the gate electrode is implanted both at the top surface and the upper portion of one side face thereof, whereas one of the source-and-drain regions is implanted with the impurity in an amount possibly attained by a single implantation, but the other portion is not implanted or only slightly implanted to a less affective degree.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2002-254672, filed on Aug. 30,2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device having a gate andsource-and-drain regions, and a method of fabricating thereof, which areparticularly preferable when applied to a CMOS transistor.

2. Description of the Related Art

Conventional CMOS transistors generally employ a polysilicon gateelectrode doped with an n-type impurity for the n-channel MOS transistor(nMOS transistor) composing thereof. This is because the thresholdvoltage can readily be controlled to desired values. The nMOS transistoris turned ON when applied with a positive voltage through the gateelectrode, which causes bending of the energy band of polysilicon, andgenerates a depletion layer within the gate electrode in the vicinity ofthe interface with a gate insulating film. Such production of thedepletion layer undesirably lowers the gate capacitance and thus reducesON current. To suppress the lowering of the gate capacitance, it isnecessary to raise concentration of the n-type impurity within the gateelectrode in the vicinity of the interface with the gate insulatingfilm.

The same will apply to the p-channel MOS transistor (pMOS transistor)which employs a polysilicon gate electrode doped with a p-type impurity,where it is also necessary to raise concentration of the p-type impuritywithin the gate electrode in the vicinity of the interface with the gateinsulating film in order to suppress lowering of the gate capacitanceduring the ON status.

In a general procedure for fabricating the aforementioned nMOS and pMOStransistors, the source-and-drain regions are formed by ionimplantation, where the gate electrodes which serve as masks are alsoconcomitantly doped.

To suppress lowering in the gate capacitance, it is necessary tosuppress formation of the depletion layer within the gate electrode, andit is thus necessary to raise the dose of the impurity introduced intothe gate electrode, which impurity is concomitantly doped also into thesource-and-drain regions. This successfully raises the impurityconcentration within the gate electrode, but also raises the impurityconcentration in the source-and-drain regions, which undesirablypromotes lateral diffusion of the impurity in the source-and-drainregions, and results in degradation of short-channel resistance.

One known solution for addressing the problem relates to reduction inheight of the gate electrode, which can substantially increase theimpurity concentration even if the dose of impurity introduced to thegate electrode remains unchanged. This solution, however, raises anotherproblem that too low height of the gate electrode may result inpunch-through of the impurity introduced into the gate electrode intothe channel, which undesirably varies the threshold voltage. Thetechnique for reducing the height of gate electrode is thus limitative.

SUMMARY OF THE INVENTION

The present invention is thus to provide a highly-reliable semiconductordevice and a method of fabricating thereof, both of which are aimed atraising impurity concentration within the gate electrode withoutincreasing impurity concentration in the source-and-drain regions, andas a consequence at improving gate capacitance and short-channelresistance without anticipating fluctuation in the threshold voltage dueto variation in shape of the gate electrode.

After extensive investigations and discussions, the present inventorsreached the various aspects of the present invention described below.

A method of fabricating a semiconductor device according to one aspectof the present invention comprises a first step of patterning a gateelectrode above a semiconductor substrate having an element isolationstructure previously formed therein; a second step of forming sidewallscovering only on both side faces of the gate electrode; a third step ofremoving the upper portion of the sidewalls to thereby expose a part ofboth side faces of the gate electrode; and a fourth step for introducingan impurity into the gate electrode along a direction inclined to thesurface of the semiconductor substrate.

A method of fabricating a semiconductor device according to anotheraspect of the present invention comprises a first step of patterning agate electrode above a semiconductor substrate; a second step of forminga mask having an opening which allows the gate electrode to be exposedtherein; and a third step of introducing an impurity into the gateelectrode along a direction inclined to the surface of the semiconductorsubstrate, wherein in the second step, the opening of the mask is formedin a size which ensures protection of areas for forming source-and-drainregions on both sides of the gate electrode from the tilt-angleintroduction of the impurity.

A semiconductor device according to one aspect of the present inventioncomprises a gate electrode; source-and-drain regions; sidewalls coveringonly the lower portion of both side faces of the gate electrode; and asilicide film formed on the exposed surface of the gate electrode,wherein the gate electrode contains an impurity having a conductivitytype same as that of the impurity contained in the source-and-drainregions, and the gate electrode has an impurity concentration largerthan that of the source-and-drain regions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view showing a major principle of afirst technique;

FIG. 2 is a schematic sectional view showing a major principle of asecond technique;

FIG. 3 is a schematic sectional view showing an exemplary case of acombination of the first and second techniques;

FIGS. 4A to 4D are schematic sectional views sequentially showingprocess steps of a method of fabricating a CMOS transistor according toa first embodiment;

FIGS. 5A to 5D are schematic sectional views sequentially showingprocess steps as continued from FIG. 4D;

FIGS. 6A and 6B are schematic sectional views sequentially showingprocess steps as continued from FIG. 5D;

FIGS. 7A to 7D are schematic sectional views sequentially showingprocess steps as continued from FIG. 6B;

FIGS. 8A to 8D are schematic sectional views sequentially showingprocess steps as continued from FIG. 7D;

FIG. 9 is a plan view for explaining tilt-angled ion implantation;

FIG. 10 is a plan view for explaining a modified example of tilt-angledion implantation in the first embodiment;

FIGS. 11A to 11D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a second embodiment;

FIGS. 12A to 12D are sequentially showing major process steps of amethod of fabricating a CMOS transistor according to a third embodiment;

FIGS. 13A to 13D are schematic sectional views sequentially showingprocess steps as continued from FIG. 12D;

FIG. 14 is a plan view for explaining tilt-angled ion implantation;

FIGS. 15A to 15D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a fourth embodiment;

FIGS. 16A to 16D are schematic sectional views sequentially showingprocess steps as continued from FIG. 15D;

FIG. 17 is a plan view for explaining tilt-angled ion implantation;

FIGS. 18A to 18D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a fifth embodiment;

FIGS. 19A to 19D are schematic sectional views sequentially showingprocess steps as continued from FIG. 18D;

FIG. 20 is a plan view for explaining tilt-angled ion implantation;

FIGS. 21A to 21D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a sixth embodiment;

FIGS. 22A to 22D are schematic sectional views sequentially showingprocess steps as continued from FIG. 21D;

FIGS. 23A to 23D are schematic sectional views sequentially showingprocess steps as continued from FIG. 22D;

FIG. 24 is a plan view for explaining tilt-angled ion implantation;

FIGS. 25A to 25D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a seventh embodiment;

FIGS. 26A to 26D are schematic sectional views sequentially showingprocess steps as continued from FIG. 25D;

FIGS. 27A to 27C are schematic sectional views sequentially showingprocess steps as continued from FIG. 26D;

FIGS. 28A to 28C are schematic sectional views sequentially showingprocess steps of a method of fabricating a CMOS transistor according toa modified example of the seventh embodiment;

FIGS. 29A to 29C are schematic sectional views sequentially showingprocess steps as continued from FIG. 28C;

FIGS. 30A to 30D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a eighth embodiment;

FIGS. 31A to 31D are schematic sectional views sequentially showingprocess steps as continued from FIG. 30D;

FIGS. 32A to 32D are schematic sectional views sequentially showingprocess steps as continued from FIG. 31D;

FIGS. 33A to 33D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a ninth embodiment;

FIGS. 34A to 34C are schematic sectional views sequentially showingprocess steps as continued from FIG. 33D;

FIG. 35 is a schematic drawing for explaining a method of determining analignment rule of a resist mask with respect to the gate electrode inthe fourth and fifth embodiments;

FIG. 36 is a schematic drawing for explaining a method of determining analignment rule of a resist mask with respect to the aligned gateelectrodes in the fourth and fifth embodiments;

FIG. 37 is a characteristic chart showing a method of determining analignment rule of a resist mask with respect to the aligned gateelectrodes in the fourth and fifth embodiments;

FIG. 38 is a schematic drawing for explaining a method of determining analignment rule of a resist mask with respect to the gate electrode inthe sixth through ninth embodiments;

FIG. 39 is a schematic drawing for explaining a method of determining analignment rule of a resist mask with respect to the aligned gateelectrodes in the sixth through ninth embodiments;

FIG. 40 is a characteristic chart showing a method of determining analignment rule of a resist mask with respect to the aligned gateelectrodes in the sixth through ninth embodiments; and

FIG. 41 is a block diagram showing an internal constitution of a generalpersonal user terminal device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

—Basic Concept of the Present Invention—

First a basic concept of a major constitution of the present inventionwill be described.

In pursuit of solving the aforementioned problems, the present inventorsreached an idea of a semiconductor device in which the gate electrode isdesigned to have an impurity concentration higher than that of thesource-and-drain regions, and proposed, as a specific technique forrealizing such semiconductor device, a method of fabricating thereof asexplained below.

(First Technique)

A major principle of a first technique is shown in FIG. 1.

First, sidewalls 103 are formed on both side faces of a gate electrode102. Portions of a semiconductor substrate 101 which fall on both sidesof the gate electrode 102 and sidewalls 103 serve as source-and-drain(S/D) regions 104, respectively.

Next, the sidewalls 103 are over-etched to thereby allow the upperportion of the gate electrode 102 to be exposed. The gate electrode 102herein is remained so as to expose an area extending from the topsurface thereof to the upper portion of both side faces thereof.

Next, an impurity having a conductivity same as that doped in thesource-and-drain regions is then implanted into the exposed surface ofthe gate electrode 102 from a direction inclined to the surface of thesemiconductor substrate 101.

The gate electrode 102 herein is doped with the impurity in its topsurface and in the upper portion of one side face (indicated withreference numeral 102 a in the figure). Since the impurity can rapidlydiffuse in polysilicon, the impurity rapidly diffuses during the laterannealing to thereby attain a uniform distribution. That is, carryingout of the tilt-angled ion implantation is nearly worth ion implantationrepeated twice, and can raise the impurity concentration at theinterface with the gate insulating film as compared with that attainableby vertical ion implantation.

On the contrary, either of the source-and-drain regions 104 isintroduced with the impurity only in a dose corresponding to a singleimplantation (indicated with reference numeral 104 a in the figure),where the other region is not introduced at all, or only slightlyintroduced (indicated with reference numeral 104 b) although beingalmost not influential.

Therefore by repeating the tilt-angled ion implantation in a pluralnumber of times, the impurity concentration of the gate electrode 102can be raised to a desired degree as compared with that of thesource-and-drain regions 104, while varying the direction ofimplantation [typically once each in the directions opposed along thewidth of the gate electrode 102 (referred to as a direction normal tothe gate length, hereinafter) and once each in the directions opposedalong the length of the gate electrode (referred to as a directionparallel to the gate length)].

(Second Technique)

A major principle of a second technique is shown in FIG. 2.

In this technique, a resist mask 105 having an opening 105 a, which isformed in a size allowing the gate electrode 102 to expose therein andallowing the source-and-drain regions 104 to be protected (prevented)from the tilt-angled ion implantation, is formed, and the tilt-angledion implantation is carried out in this situation. Also in this case,the tilt-angled ion implantation is carried out in a plural number oftimes while varying the direction of implantation.

The gate electrode 102 herein is doped with the impurity in its topsurface and in the upper portion of one side face (indicated withreference numeral 102 a in the figure). Since the impurity can rapidlydiffuse in polysilicon, the impurity rapidly diffuses during the laterannealing to thereby attain a uniform distribution. That is, a singletilt-angled ion implantation is nearly worth ion implantation repeatedtwice, and can raise the impurity concentration at the interface withthe gate insulating film as compared with that attainable by verticalion implantation.

On the contrary, a pair of source-and-drain regions 104 protected by theresist mask 105 are prevented from being introduced with the impurity.

Since increase in the impurity concentration in the gate electrode 102does not affect or increase the impurity concentration of thesource-and-drain regions 104 as described in the above, short-channeleffect is certainly prevented from being worsened.

It is to be noted now that it is also allowable, as shown in FIG. 3, toover-etch the sidewalls 103 so as to expose the upper portion of bothside faces of the gate electrode 102 as described in the firsttechnique, and then to form the resist mask 105 having the opening 105 aformed in a size which ensures protection (prevention) of thesource-and-drain regions 104 from the tilt-angled ion implantation asdescribed in the second technique, and to carry out the tilt-angled ionimplantation in this situation. This ensures introduction of theimpurity only into the gate electrode 102 in a more precise manner.

Specific Embodiments

Based on the basic concept of the present invention described in theabove, specific embodiments whereby the present invention is applied toa CMOS transistor will be explained with reference to the attacheddrawings.

First Embodiment

FIGS. 4A through 8D are schematic sectional views sequentially showingprocess steps of a method of fabricating a CMOS transistor.

First as shown in FIG. 4A, trenches are formed in an element isolationregion of a semiconductor substrate 1, filled with an insulatingmaterial such as silicon oxide, and the surface thereof is planarizedtypically by CMP (chemical mechanical polishing) to thereby form aSTI-type (shallow trench isolation-type) element isolation structures 2.This partitions element active regions on the semiconductor substrate 1,which are an nMOS region 11 and a pMOS region 12.

Next, as shown in FIG. 4B, a resist mask 13 is formed so as to cover thepMOS region 12, and a p-type impurity is introduced by ion implantationinto the nMOS region 11, to thereby form a p-well 3, and a channelstopper layer (not shown) in the surficial portion of the substrate.

Next, the resist mask 13 is removed typically by ashing, a resist mask14 is formed so as to cover the nMOS region 11 as shown in FIG. 4C, andan n-type impurity is introduced by ion implantation into the PMOSregion 12, to thereby form an n-well 4, and a channel stopper layer (notshown) in the surficial portion of the substrate.

Next, the resist mask 14 is removed typically by ashing, and, as shownin FIG. 4D, the semiconductor substrate 1 is then annealed by RTA (rapidthermal annealing) at 1,000° C. for 3 seconds to thereby restore thesubstrate from damage caused by introduction of the impurities into thewells 3, 4 and channel stopper layers.

Next, as shown in FIG. 5A, a thin gate insulating film 5 is formed onthe surface of the semiconductor substrate 1 by thermal oxidation, andfurther thereon, a non-doped polysilicon film 15 is deposited by the CVDprocess as shown in FIG. 5B.

Next, the polysilicon film 15 and the gate insulating film 5 arepatterned by photolithography and succeeding dry etching to thereby formgate electrodes 6 a, 6 b of approx. 100 nm high and approx. 50 nm wideon the gate insulating film 5 in the nMOS and PMOS regions 11, 12,respectively, as shown in FIG. 5C. In this process, the polysilicon film15 has no impurity previously introduced therein, because polysilicondoped with an n-type impurity and that doped with a p-type impuritygenerally differ in the etchrate, which makes it difficult to formrespective gate electrodes of nMOS transistor and pMOS transistor at asame time.

Next, as shown in FIG. 5D, a resist mask 16 is formed so as to cover thePMOS region 12, and an n-type impurity, which is arsenic (As) herein, isintroduced by vertical ion implanted into the nMOS region 11 at an ionacceleration energy of 5 keV and a dose of 6×10¹⁴/cm², and also a p-typeimpurity, which is boron (B) herein, is introduced by ion implantationat an ion acceleration energy of 10 keV, a dose of 8×10¹²/cm², and anangle of incidence of 30° from four directions, to thereby form n-typeextension layers 7 a and p-type pocket layers 8 a, respectively.

Next, the resist mask 16 is removed typically by ashing, a resist mask17 is formed so as to cover the nMOS region 11 as shown in FIG. 6A, anda p-type impurity, which is boron (B) herein, is introduced by verticalion implantation into the pMOS region 12 at an ion acceleration energyof 0.5 keV and a dose of 6×10¹⁴/cm², and also an n-type impurity, whichis arsenic (As) herein, is introduced by ion implantation at an ionacceleration energy of 50 keV, a dose of 6×10¹²/cm², and an angle ofincidence of 30° from four directions, to thereby form p-type extensionlayers 7 b and n-type pocket layers 8 a, respectively.

Next, as shown in FIG. 6B, the resist mask 17 is removed typically byashing, and, as shown in FIG. 6B, the semiconductor substrate 1 is thenannealed by RTA (rapid thermal annealing) at 1,000° C. for one second tothereby restore the substrate from damage generated by introduction ofthe impurities into the extension layers 7 a, 7 b and pocket layers 8 a,8 b.

Next, a silicon oxide film (not shown) is deposited on the entiresurface by the CVD process, and the film is then anisotropically etchedback so as to allow the film to remain only on both side faces of thegate electrodes 6 a, 6 b, to thereby form sidewalls 9 a, 9 b having amaximum width of 80 nm or around, as shown in FIG. 7A.

Next, a resist mask 18 is formed so as to cover the pMOS region 12 asshown in FIG. 7B, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 4.5×10¹⁵/cm² and an angle ofincidence of 0° (that is, normal to the surface of the substrate), tothereby form the n-type, source-and-drain regions 10 a. Phosphorusherein is also implanted into the gate electrode 6 a. The dose ofphosphorus in this process is controlled to a smaller value (6×10¹⁵/cm²,for example) than that in general formation process of n-type,source-and-drain regions.

Next, the resist mask 18 is removed typically by ashing, a resist mask19 is formed so as to cover the nMOS region 11 as shown in FIG. 7C, anda p-type impurity, which is boron (B) herein, is introduced by ionimplantation into the pMOS region 12 at an ion acceleration energy of 4keV, a dose of 2.25×10¹⁵/cm² and an angle of incidence of 0°, to therebyform the p-type, source-and-drain regions 10 b. Boron herein is alsoimplanted into the gate electrode 6 b. The dose of boron in this processis controlled to a smaller value (3×10¹⁵/cm², for example) than that ingeneral formation process of p-type, source-and-drain regions.

Next, the resist mask 19 is removed typically by ashing, and thesidewalls 9 a, 9 b are dry-etched (over-etched) to thereby allow theupper portion of both side faces of the gate electrodes 6 a, 6 b toexpose as much as 50 nm or around as shown in FIG. 7D. The gateelectrodes 6 a, 6 b herein are remained so as to expose an areaextending from the top surface thereof to the upper portion of both sidefaces thereof, and the sidewalls 9 a, 9 b are adjusted so as to have aheight of 50 nm or around.

Considering now that the gate electrodes 6 a, 6 b are subjected totilt-angled ion implantation described later, the more the sidewalls 9a, 9 b are etched, the more the gate electrodes 6 a, 6 b will have animpurity incorporated therein. Too much amount of etching of thesidewalls 9 a, 9 b may, however, result in excessive diffusion of theincorporated impurities in the source-and-drain regions 10 a, 10 btowards the channel, or may raise a risk of short-circuiting betweensilicides, which are formed later on the source-and-drain regions 10 a,10 b and on the gate electrodes 6 a, 6 b. Thus there is an appropriaterange for the amount of etching of the sidewalls 9 a, 9 b, and 50 nm isone exemplary amount falls within such range.

To prevent the STI-type element isolation structure 2 from being etchedtogether with the sidewalls 9 a, 9 b, it is preferable to use differentmaterials to form the sidewalls 9 a, 9 b and STI-type element isolationstructure 2 so that the sidewalls 9 a, 9 b will have a higher etchratethan that of the element isolation structure 2. One preferable exampleis such that using a plasma oxide film formed in an HDP (high densityplasma) apparatus for the STI-type element isolation structure 2 andusing an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls 9 a, 9 b.

Next, as shown in FIG. 8A, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a).

More specifically, a resist mask 21 is formed so as to cover the pMOSregion 12, and an n-type impurity, which is phosphorus (P) herein, isimplanted at an ion acceleration energy of 4 keV, a dose of 5×10¹⁴/cm²,and an angle of incidence of 45°. The implantation is repeated fourtimes (twice in two opposing directions parallel to the gate length andtwice in two opposing directions normal thereto). The ion implantationrepeated four times is shown in a schematic plan view in FIG. 9.

FIG. 8A shows an exemplary ion implantation effected along a directionparallel to the gate length and at an angle of incidence of 45°. Sincethe top surface and the upper portion of one side face of the gateelectrode 6 a herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 a in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice, and also results in introduction of theimpurity into one n-type, source-and-drain region 10 a in an amountequivalent to that possibly attained by a single ion implantation at anangle of incidence of 0°. Another n-type, source-and-drain region 10 a,which is shadowed by the gate electrode 6 a, is not introduced with theimpurity, or introduced only in a less affective amount.

Although not being illustrated for convenience, a single ionimplantation normal to the gate length at an angle of incidence of 45°results in introduction of the impurity into the gate electrode 6 a inan amount equivalent to that possibly attained by a single ionimplantation at an angle of incidence of 0°, and also results inintroduction of the impurity into both n-type, source-and-drain regions10 a in an amount again equivalent to that possibly attained by a singleion implantation at an angle of incidence of 0°.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 a will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (5×10¹⁴/cm²) repeated sixtimes, in addition to a dose of 4.5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of phosphorus of 7.5×10¹⁵/cm².On the contrary, each n-type, source-and-drain region 10 a will haveintroduced therein the impurity in an amount equivalent to that possiblyattained by ion implantations at an angle of incidence of 0° repeatedthree times, in addition to a dose of 4.5×10¹⁵/cm² which has previouslybeen attained, and thus will have a total dose of phosphorus of6×10¹⁵/cm² (same level with that of general source-and-drain region).

In the aforementioned process for forming the n-type, source-and-drainregion 10 a, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 8 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 4 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 a, to prevent the impurity frompenetrating the sidewall 10 a and gate electrode 6 a and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the n-type, source-and-drain region 10 a from diffusing toward thechannel.

Next, as shown in FIG. 8B, a p-type impurity is implanted into the pMOSregion 12 to thereby introduce the impurity to the exposed surface ofthe gate electrode 6 b (the top surface of 50 nm wide and both sidefaces of 50 nm high exposed from the sidewall 9 b).

More specifically, a resist mask 21 is removed typically by ashing, anda resist mask 22 is formed so as to cover the nMOS region 11, and ap-type impurity, which is boron (B) herein, is implanted at an ionacceleration energy of 2 keV, a dose of 2.5×10¹⁴/cm², and an angle ofincidence of 45°. The implantation is repeated four times (twice in twoopposing directions parallel to the gate length and twice in twoopposing directions normal thereto).

FIG. 8B shows an exemplary ion implantation effected along a directionparallel to the gate length and at an angle of incidence of 45°. Sincethe top surface and the upper portion of one side face of the gateelectrode 6 b herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 b in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice, and also results in introduction of theimpurity into one p-type, source-and-drain region 10 b in an amountequivalent to that possibly attained by a single ion implantation at anangle of incidence of 0°. Another p-type, source-and-drain region 10 b,which is shadowed by the gate electrode 6 b, is not introduced with theimpurity, or introduced only in a less affective amount.

Although not being illustrated for convenience, a single ionimplantation normal to the gate length at an angle of incidence of 45°results in introduction of the impurity into the gate electrode 6 b inan amount equivalent to that possibly attained by a single ionimplantation at an angle of incidence of 0°, and also results inintroduction of the impurity into both p-type, source-and-drain regions10 b in an amount again equivalent to that possibly attained by a singleion implantation at an angle of incidence of 0°.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 b will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (2.5×10¹⁴/cm²) repeated sixtimes, in addition to a dose of 2.25×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of boron of 3.75×10¹⁵/cm². Onthe contrary, each p-type, source-and-drain region 10 b will haveintroduced therein the impurity in an amount equivalent to that possiblyattained by ion implantations at an angle of incidence of 0° repeatedthree times, in addition to a dose of 2.25×10¹⁵/cm² which has previouslybeen attained, and thus will have a total dose of boron of 3×10¹⁵/cm²(same level with that of general source-and-drain region).

In the aforementioned process for forming the p-type, source-and-drainregion 10 b, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 4 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 2 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 b, to prevent the impurity frompenetrating the sidewall 10 b and gate electrode 6 b and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the p-type, source-and-drain region 10 b from diffusing toward thechannel.

Next, the resist mask 22 is removed typically by ashing, and, as shownin FIG. 8C, the semiconductor substrate 1 is then annealed by RTA (rapidthermal annealing) at 1,030° C. for one second to thereby restore itfrom damage caused by ion implantation into the gate electrodes 6 a, 6 band source-and-drain regions 10 a, 10 b, and to thereby activate theimpurities.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 8D.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the first embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b by formingthe sidewalls 9 a, 9 a so as to expose the upper portion of the gateelectrodes 6 a, 6 b, and by carrying out the ion implantation at anangle of incidence of 45°. In the first embodiment, the impurityconcentration of the gate electrodes 6 a, 6 b becomes higher than thatof the source-and-drain regions 10 a, 10 b by approx. 25%, where theimpurity concentration of the gate electrodes 6 a, 6 b can be raisedwhile keeping the general impurity concentration of the source-and-drainregions 10 a, 10 b unchanged. The present embodiment is thus to providea highly-reliable CMOS transistor having an improved gate capacitanceand short-channel resistance without anticipating fluctuation in thethreshold voltage due to variation in shape of the gate electrode.

(Modified Example)

A modified example of the present embodiment will be described.

The present invention is by no means limited to mode of the ionimplantation in the first embodiment described in the above, whereconditions for the first ion implantation for forming thesource-and-drain regions or successive tilt-angled ion implantations canproperly be selected provided that the impurity concentration of thegate electrodes can be raised without increasing the impurityconcentration of the source-and-drain regions.

For example, in this modified example, as shown in FIG. 10, the firstion implantation of phosphorus for forming the n-type, source-and-drainregion 10 a is carried out at an ion acceleration energy of 8 keV, adose of 5.5×10¹⁵/cm² and an angle of incidence of 0°, and thetilt-angled ion implantation of phosphorus is carried out twice alongthe direction parallel to the gate length respectively at an ionacceleration energy of 4 keV, a dose of 5×10¹⁴/cm² and an angle ofincidence of 45°.

By the ion implantation repeated twice, as shown later in Table 1, thegate electrode 6 a will have introduced therein the impurity in anamount equivalent to that possibly attained by ion implantations at anangle of incidence of 0° (5×10¹⁴/cm²) repeated four times, in additionto a dose of 5.5×10⁻⁵/cm² which has previously been attained, and thuswill have a total dose of phosphorus of 7.5×10¹⁵/cm². On the contrary,each n-type, source-and-drain region 10 a will have introduced thereinthe impurity in an amount equivalent to that possibly attained by asingle ion implantation at an angle of incidence of 0°, in addition to adose of 5.5×10¹⁵/cm² which has previously been attained, and thus willhave a total dose of phosphorus of 6×10¹⁵/cm² (same level with that ofgeneral source-and-drain region).

Similarly to the above, the first ion implantation of boron for formingthe p-type, source-and-drain region 10 b is carried out at an ionacceleration energy of 4 keV, a dose of 2.75×10¹⁵/cm² and an angle ofincidence of 0°, and the tilt-angled ion implantation of phosphorus iscarried out twice along the direction parallel to the gate lengthindividually at an ion acceleration energy of 2 keV, a dose of2.5×10¹⁴/cm² and an angle of incidence of 45°.

By the ion implantation repeated twice, as shown later in Table 1, thegate electrode 6 b will have introduced therein the impurity in anamount equivalent to that possibly attained by ion implantations at anangle of incidence of 0° (2.5×10¹⁴/cm²) repeated four times, in additionto a dose of 2.75×10¹⁵/cm² which has previously been attained, and thuswill have a total dose of boron of 3.75×10¹⁵/cm². On the contrary, eachp-type, source-and-drain region 10 b will have introduced therein theimpurity in an amount equivalent to that possibly attained by a singleion implantation at an angle of incidence of 0°, in addition to a doseof 2.75×10¹⁵/cm² which has previously been attained, and thus will havea total dose of boron of 3×10¹⁵/cm² (same level with that of generalsource-and-drain region).

Second Embodiment

FIGS. 11A to 11D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a second embodiment.

In the second embodiment, the individual process steps previously shownin FIGS. 4A through 8B are executed to thereby control the dose ofphosphorus to 7.5×10¹⁵/cm² for the gate electrode 6 a and 6×10¹⁵/cm² forthe n-type, source-and-drain region 10 a in the nMOS region 11, and thedose of boron to 3.75×10¹⁵/cm² for the gate electrode 6 b and 3×10¹⁵/cm²for the p-type, source-and-drain region 10 b in the pMOS region 12. Thesemiconductor substrate 1 is then annealed by RTA at 1,030° C. for 1second (FIG. 11A).

Next, as shown in FIG. 11B, a silicon oxide film 27 is formed over theentire surface by the CVD process, and then as shown in FIG. 1C, thesilicon oxide film 27 is then anisotropically etched back so as to allowthe film to remain only on both side faces of the gate electrodes 6 a, 6b, to thereby form sidewalls 9 a, 9 b. That is, the sidewalls 9 a, 9 bnow recover the status previously shown in FIG. 7A.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 11D.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the second embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b by formingthe sidewalls 9 a, 9 a so as to expose the upper portion of the gateelectrodes 6 a, 6 b, and by carrying out the ion implantation at anangle of incidence of 45°. In the second embodiment, the impurityconcentration of the gate electrodes 6 a, 6 b becomes higher than thatof the source-and-drain regions 10 a, 10 b by approx. 25%, where theimpurity concentration of the gate electrodes 6 a, 6 b can be raisedwhile keeping the general impurity concentration of the source-and-drainregions 10 a, 10 b unchanged. The present embodiment is thus to providea highly-reliable CMOS transistor having an improved gate capacitanceand short-channel resistance without anticipating fluctuation in thethreshold voltage due to variation in shape of the gate electrode.

The second embodiment is also successful in certainly preventshort-circuiting between CoSi₂ formed on the source-and-drain regions 10a, 10 b and CoSi₂ formed on the gate electrodes 6 a, 6 b, since thesidewalls 9 a, 9 b recover their initial form almost completely coveringthe side faces of the gate electrodes before the CoSi₂ layer 23 isformed. Thus the sidewalls 9 a, 9 b can thoroughly be over-etched inpreparation for the tilt-angled ion implantation without anticipatingthe short-circuiting. It is therefore also preferable to raise theamount of over-etching larger than that in the first embodiment (50%),to thereby further increase dose of implanted ion in the gate electrodes6 a, 6 b.

Also in the second embodiment, similarly to the modified example of thefirst embodiment, conditions for the first ion implantation for formingthe source-and-drain regions or successive tilt-angled ion implantationscan properly be selected provided that the impurity concentration of thegate electrodes can be raised without increasing the impurityconcentration of the source-and-drain regions.

For example, the first ion implantation of phosphorus for forming then-type, source-and-drain region 10 a is carried out at an ionacceleration energy of 8 keV, a dose of 5.5×10¹⁵/cm² and an angle ofincidence of 0°, and the tilt-angled ion implantation of phosphorus iscarried out twice along the direction parallel to the gate lengthrespectively at an ion acceleration energy of 4 keV, a dose of5×10¹⁴/cm² and an angle of incidence of 45°.

By the ion implantation repeated twice, as shown later in Table 1, thegate electrode 6 a will have introduced therein the impurity in anamount equivalent to that possibly attained by ion implantations at anangle of incidence of 0° (5×10¹⁴/cm²) repeated four times, in additionto a dose of 5.5×10¹⁵/cm² which has previously been attained, and thuswill have a total dose of phosphorus of 7.5×10¹⁵/cm². On the contrary,each n-type, source-and-drain region 10 a will have introduced thereinthe impurity in an amount equivalent to that possibly attained by asingle ion implantation at an angle of incidence of 0°, in addition to adose of 5.5×10¹⁵/cm² which has previously been attained, and thus willhave a total dose of phosphorus of 6×10¹⁵/cm² (same level with that ofgeneral source-and-drain region).

Similarly to the above, the first ion implantation of boron for formingthe p-type, source-and-drain region 10 b is carried out at an ionacceleration energy of 4 keV, a dose of 2.75×10¹⁵/cm² and an angle ofincidence of 0°, and the tilt-angled ion implantation of boron iscarried out twice along the direction parallel to the gate lengthrespectively at an ion acceleration energy of 2 keV, a dose of2.5×10¹⁴/cm² and an angle of incidence of 45°.

By the ion implantation repeated twice, as shown later in Table 1, thegate electrode 6 b will have introduced therein the impurity in anamount equivalent to that possibly attained by ion implantations at anangle of incidence of 0° (2.5×10¹⁴/cm²) repeated four times, in additionto a dose of 2.75×10¹⁵/cm² which has previously been attained, and thuswill have a total dose of boron of 3.75×10¹⁵/cm². On the contrary, eachp-type, source-and-drain region 10 b will have introduced therein theimpurity in an amount equivalent to that possibly attained by a singleion implantation at an angle of incidence of 0°, in addition to a doseof 2.75×10¹⁵/cm² which has previously been attained, and thus will havea total dose of boron of 3×10¹⁵/cm² (same level with that of generalsource-and-drain region).

Third Embodiment

FIGS. 12A through 13D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a third embodiment.

In the third embodiment, the individual process steps previously shownin FIGS. 4A through 6B are executed to thereby form the sidewalls 9 a, 9b which cover both side faces of the gate electrodes 6 a, 6 b and havinga maximum width of 80 nm or around (FIG. 12A).

Next, as shown in FIG. 12B, the resist mask 18 is formed so as to coverthe pMOS region 12, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 5×10¹⁵/cm², and an angle ofincidence of 0°, to thereby form the n-type, source-and-drain regions 10a. Phosphorus herein is also implanted into the gate electrode 6 a. Thedose of phosphorus in this process is controlled to a smaller value(6×10¹⁵/cm², for example) than that in general formation process ofn-type, source-and-drain regions.

Next, the resist mask 18 is removed typically by ashing, the resist mask19 is formed so as to cover the nMOS region 11 as shown in FIG. 12C, anda p-type impurity, which is boron (B) herein, is introduced by ionimplantation into the pMOS region 12 at an ion acceleration energy of 4keV, a dose of 2.5×10¹⁵/cm² and an angle of incidence of 0°, to therebyform the p-type, source-and-drain regions 10 b. Boron herein is alsoimplanted into the gate electrode 6 b. The dose of boron in this processis controlled to a smaller value (3×10⁵/cm², for example) than that ingeneral formation process of p-type, source-and-drain regions.

Next, the resist mask 19 is removed typically by ashing, and thesidewalls 9 a, 9 b are dry-etched (over-etched) to thereby allow theupper portion of both side faces of the gate electrodes 6 a, 6 b toexpose as much as 50 nm or around as shown in FIG. 12D. The gateelectrodes 6 a, 6 b herein are remained so as to expose an areaextending from the top surface thereof to the upper portion of both sidefaces thereof, and the sidewalls 9 a, 9 b are adjusted so as to have aheight of 50 nm or around.

Considering now that the gate electrodes 6 a, 6 b are subjected totilt-angled ion implantation described later, the more the sidewalls 9a, 9 b are etched, the more the gate electrodes 6 a, 6 b will have animpurity incorporated therein. Too much amount of etching of thesidewalls 9 a, 9 b may, however, result in excessive diffusion of theincorporated impurity in the source-and-drain regions 10 a, 10 b towardsthe channel, or may raise a risk of short-circuiting between silicides,which are formed later on the source-and-drain regions 10 a, 10 b and onthe gate electrodes 6 a, 6 b. Thus there is an appropriate range for theamount of etching of the sidewalls 9 a, 9 b, and 50 nm is one exemplaryamount falls within such range.

To prevent the STI-type element isolation structure 2 from being etchedtogether with the sidewalls 9 a, 9 b, it is preferable to use differentmaterials to form the sidewalls 9 a, 9 b and STI-type element isolationstructure 2 so that the sidewalls 9 a, 9 b will have a higher etchratethan that of the element isolation structure 2. One preferable exampleis such that using a plasma oxide film formed in an HDP (high densityplasma) apparatus for the STI-type element isolation structure 2 andusing an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls 9 a, 9 b.

Next, as shown in FIG. 13A, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a).

More specifically, the resist mask 21 is formed so as to cover the pMOSregion 12, and an n-type impurity, which is phosphorus (P) herein, isimplanted at an ion acceleration energy of 4 keV, a dose of 5×10¹⁴/cm²,and an angle of incidence of 45°. The implantation is repeated fourtimes from directions differing from each other (four differentdirections inclined by 45° away from the direction of gate length). Theion implantation repeated four times is shown in a schematic plan viewin FIG. 14.

Since the top surface and the upper portion of one side face of the gateelectrode 6 a herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 a in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice, and also results in introduction of theimpurity into one n-type, source-and-drain region 10 a in an amountequivalent to that possibly attained by a single ion implantation at anangle of incidence of 0°. Another n-type, source-and-drain region 10 a,which is shadowed by the gate electrode 6 a, is not introduced with theimpurity, or introduced only in a less affective amount.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 a will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (5×10¹⁴/cm²) repeated eighttimes, in addition to a dose of 5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of phosphorus of 9×10¹⁵/cm².On the contrary, each n-type, source-and-drain region 10 a will haveintroduced therein the impurity in an amount equivalent to that possiblyattained by ion implantations at an angle of incidence of 0° repeatedtwice, in addition to a dose of 5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of phosphorus of 6×10¹⁵/cm²(same level with that of general source-and-drain region).

In the aforementioned process for forming the n-type, source-and-drainregion 10 a, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 8 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 4 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 a, to prevent the impurity frompenetrating the sidewall 10 a and gate electrode 6 a and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the n-type, source-and-drain region 10 a from diffusing toward thechannel.

Next, as shown in FIG. 13B, a p-type impurity is implanted into the pMOSregion 12 to thereby introduce the impurity to the exposed surface ofthe gate electrode 6 b (the top surface of 50 nm wide and both sidefaces of 50 nm high exposed from the sidewall 9 b).

More specifically, the resist mask 21 is removed typically by ashing,and the resist mask 22 is formed so as to cover the nMOS region 11, anda p-type impurity, which is boron (B) herein, is implanted at an ionacceleration energy of 2 keV, a dose of 2.5×10¹⁴/cm², and an angle ofincidence of 45°. The implantation is repeated four times fromdirections differing from each other (four different directions inclinedby 45° away from the direction of gate length).

Since the top surface and the upper portion of one side face of the gateelectrode 6 b herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 b in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice, and also results in introduction of theimpurity into one p-type, source-and-drain region 10 b in an amountequivalent to that possibly attained by a single ion implantation at anangle of incidence of 0°. Another p-type, source-and-drain region 10 b,which is shadowed by the gate electrode 6 b, is not introduced with theimpurity, or introduced only in a less affective amount.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 b will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (2.5×10¹⁴/cm²) repeatedeight times, in addition to a dose of 2.5×10¹⁵/cm² which has previouslybeen attained, and thus will have a total dose of boron of 4.5×10¹⁵/cm².On the contrary, each p-type, source-and-drain region 10 b will haveintroduced therein the impurity in an amount equivalent to that possiblyattained by ion implantations at an angle of incidence of 0° repeatedtwice, in addition to a dose of 2.5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of boron of 3×10¹⁵/cm² (samelevel with that of general source-and-drain region).

In the aforementioned process for forming the p-type, source-and-drainregion 10 b, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 4 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 2 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 b, to prevent the impurity frompenetrating the sidewall 10 b and gate electrode 6 b and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the p-type, source-and-drain region 10 b from diffusing toward thechannel.

Next, the resist mask 22 is removed typically by ashing, and, as shownin FIG. 13C, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,030° C. for one second to thereby restoreit from damage caused by ion implantation into the gate electrodes 6 a,6 b and source-and-drain regions 10 a, 10 b, and to thereby activate theimpurities.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 13D.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the third embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b by formingthe sidewalls 9 a, 9 a so as to expose the upper portion of the gateelectrodes 6 a, 6 b, and by carrying out the ion implantation from fourinclined directions at an angle of incidence of 45°. In the thirdembodiment, the impurity concentration of the gate electrodes 6 a, 6 bbecomes higher than that of the source-and-drain regions 10 a, 10 b byapprox. 50%, where the impurity concentration of the gate electrodes 6a, 6 b can be raised while keeping the general impurity concentration ofthe source-and-drain regions 10 a, 10 b unchanged. The third embodimentis thus to provide a highly-reliable CMOS transistor having an improvedgate capacitance and short-channel resistance without anticipatingfluctuation in the threshold voltage due to variation in shape of thegate electrode.

Fourth Embodiment

FIGS. 15A through 16D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a fourth embodiment.

In the fourth embodiment, the individual process steps previously shownin FIGS. 4A through 6B are executed to thereby form the sidewalls 9 a, 9b which cover both side faces of the gate electrodes 6 a, 6 b and havinga maximum width of 80 nm or around (FIG. 15A).

Next, as shown in FIG. 15B, the resist mask 18 is formed so as to coverthe pMOS region 12, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 5×10¹⁵/cm², and an angle ofincidence of 0°, to thereby form the n-type, source-and-drain regions 10a. Phosphorus herein is also implanted into the gate electrode 6 a. Thedose of phosphorus in this process is controlled to a smaller value(6×10¹⁵/cm², for example) than that in general formation process ofn-type, source-and-drain regions.

Next, the resist mask 18 is removed typically by ashing, the resist mask19 is formed so as to cover the nMOS region 11 as shown in FIG. 15C, anda p-type impurity, which is boron (B) herein, is introduced by ionimplantation into the pMOS region 12 at an ion acceleration energy of 4keV, a dose of 2.5×10¹⁵/cm² and an angle of incidence of 0°, to therebyform the p-type, source-and-drain regions 10 b. Boron herein is alsoimplanted into the gate electrode 6 b. The dose of boron in this processis controlled to a smaller value (3×10¹⁵/cm², for example) than that ingeneral formation process of p-type, source-and-drain regions.

Next, the resist mask 19 is removed typically by ashing, and thesidewalls 9 a, 9 b are dry-etched (over-etched) to thereby allow theupper portion of both side faces of the gate electrodes 6 a, 6 b toexpose as much as 50 nm or around as shown in FIG. 15D. The gateelectrodes 6 a, 6 b herein are remained so as to expose an areaextending from the top surface thereof to the upper portion of both sidefaces thereof, and the sidewalls 9 a, 9 b are adjusted so as to have aheight of 50 nm or around.

Considering now that the gate electrodes 6 a, 6 b are subjected totilt-angled ion implantation described later, the more the sidewalls 9a, 9 b are etched, the more the gate electrodes 6 a, 6 b will have animpurity incorporated therein. Too much amount of etching of thesidewalls 9 a, 9 b may, however, result in excessive diffusion of theincorporated impurity in the source-and-drain regions 10 a, 10 b towardsthe channel, or may raise a risk of short-circuiting between silicides,which are formed later on the source-and-drain regions 10 a, 10 b and onthe gate electrodes 6 a, 6 b. Thus there is an appropriate range for theamount of etching of the sidewalls 9 a, 9 b, and 50 nm is one exemplaryamount falls within such range.

To prevent the STI-type element isolation structure 2 from being etchedtogether with the sidewalls 9 a, 9 b, it is preferable to use differentmaterials to form the sidewalls 9 a, 9 b and STI-type element isolationstructure 2 so that the sidewalls 9 a, 9 b will have a higher etchratethan that of the element isolation structure 2. One preferable exampleis such that using a plasma oxide film formed in an HDP (high densityplasma) apparatus for the STI-type element isolation structure 2 andusing an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls 9 a, 9 b.

Next, as shown in FIG. 16A, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a).

More specifically, a resist mask 31 is formed so as to cover the PMOSregion 12, which mask 31 having an opening 31 a formed in a size capableof protecting the n-type, source-and-drain regions 10 a from thetilt-angled ion implantation. The resist mask 31 herein is approx. 120nm high, and the opening 31 a has an edge 120 nm away from the edge ofthe gate electrode 6 a. In alignment of a reticle for forming theopening 31 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. An n-type impurity, which isphosphorus (P) herein, is implanted into the nMOS region 11 at an ionacceleration energy of 4 keV, a dose of 5×10¹⁴/cm², and an angle ofincidence of 45°. The implantation is repeated four times from fourdirections differing from each other (twice in two opposing directionsparallel to the gate length and twice in two opposing directions normalthereto). The ion implantation repeated four times is shown in aschematic plan view in FIG. 17.

FIG. 16A shows an exemplary ion implantation effected along a directionparallel to the gate length and at an angle of incidence of 45°. Sincethe top surface and the upper portion of one side face of the gateelectrode 6 a herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 a in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice. On the other hand, a pair of n-type,source-and-drain regions 10 a are protected by the resist mask 31against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Although not being illustrated for convenience, a single ionimplantation normal to the gate length at an angle of incidence of 45°results in introduction of the impurity into the gate electrode 6 a inan amount equivalent to that possibly attained by a single ionimplantation at an angle of incidence of 0°, and also results inintroduction of the impurity into both n-type, source-and-drain regions10 a in an amount again equivalent to that possibly attained by a singleion implantation at an angle of incidence of 0°.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 a will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (5×10¹⁴/cm²) repeated sixtimes, in addition to a dose of 5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of phosphorus of 8×10¹⁵/cm².On the contrary, each n-type, source-and-drain region 10 a will haveintroduced therein the impurity in an amount equivalent to that possiblyattained by ion implantations at an angle of incidence of 0° repeatedtwice, in addition to a dose of 5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of phosphorus of 6×10¹⁵/cm²(same level with that of general source-and-drain region).

In the aforementioned process for forming the n-type, source-and-drainregion 10 a, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 8 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 4 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 a, to prevent the impurity frompenetrating the sidewall 10 a and gate electrode 6 a and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the n-type, source-and-drain region 10 a from diffusing toward thechannel.

Next, as shown in FIG. 16B, a p-type impurity is implanted along adirection inclined into the pMOS region 12 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 b (the topsurface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 b).

More specifically, the resist mask 31 is removed typically by ashing,and a resist mask 32 is formed so as to cover the nMOS region 11, whichmask 32 having an opening 32 a formed in a size capable of protectingthe p-type, source-and-drain regions 10 b from the tilt-angled ionimplantation. The resist mask 32 herein is approx. 120 nm high, and theopening 32 a has an edge 120 nm away from the edge of the gate electrode6 b. In alignment of a reticle for forming the opening 31 a byphotolithography, employing the gate electrode as an alignment mark, inplace of a mark formed in the STI process, can successfully reducemis-alignment. A p-type impurity, which is boron (B) herein, isimplanted into the pMOS region 12 at an ion acceleration energy of 2keV, a dose of 2.5×10¹⁴/cm², and an angle of incidence of 45°. Theimplantation is repeated four times from four directions differing fromeach other (twice in two opposing directions parallel to the gate lengthand twice in two opposing directions normal thereto).

FIG. 16B shows an exemplary ion implantation effected along a directionparallel to the gate length and at an angle of incidence of 45°. Sincethe top surface and the upper portion of one side face of the gateelectrode 6 b herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 b in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice. On the other hand, a pair of p-type,source-and-drain regions 10 b are protected by the resist mask 32against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Although not being illustrated for convenience, a single ionimplantation normal to the gate length at an angle of incidence of 45°results in introduction of the impurity into the gate electrode 6 b inan amount equivalent to that possibly attained by a single ionimplantation at an angle of incidence of 0°, and also results inintroduction of the impurity into both p-type, source-and-drain regions10 b in an amount again equivalent to that possibly attained by a singleion implantation at an angle of incidence of 0°.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 b will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (2.5×10¹⁴/cm²) repeated sixtimes, in addition to a dose of 2.5×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of boron of 4×10¹⁵/cm². On thecontrary, each p-type, source-and-drain region 10 b will have introducedtherein the impurity in an amount equivalent to that possibly attainedby ion implantations at an angle of incidence of 0° repeated twice, inaddition to a dose of 2.5×10¹⁵/cm² which has previously been attained,and thus will have a total dose of boron of 3×10¹⁵/cm² (same level withthat of general source-and-drain region).

In the aforementioned process for forming the p-type, source-and-drainregion 10 b, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 4 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 2 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 b, to prevent the impurity frompenetrating the sidewall 10 b and gate electrode 6 b and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the p-type, source-and-drain region 10 b from diffusing toward thechannel.

Next, the resist mask 32 is removed typically by ashing, and, as shownin FIG. 16C, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,030° C. for one second to thereby restoreit from damage caused by ion implantation into the gate electrodes 6 a,6 b and source-and-drain regions 10 a, 10 b, and to thereby activate theimpurities.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 16D.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the fourth embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b by formingthe sidewalls 9 a, 9 a so as to expose the upper portion of the gateelectrodes 6 a, 6 b, and by carrying out the ion implantation from fourinclined directions at an angle of incidence of 45°. In the fourthembodiment, the impurity concentration of the gate electrodes 6 a, 6 bbecomes higher than that of the source-and-drain regions 10 a, 10 b byapprox. 33%, where the impurity concentration of the gate electrodes 6a, 6 b can be raised while keeping the general impurity concentration ofthe source-and-drain regions 10 a, 10 b unchanged. The fourth embodimentis thus to provide a highly-reliable CMOS transistor having an improvedgate capacitance and short-channel resistance without anticipatingfluctuation in the threshold voltage due to variation in shape of thegate electrode.

Moreover in the tilt-angled ion implantation, the source-and-drainregions 10 a, 10 b are successfully prevented from being implanted withthe impurities by virtue of the resist masks 31, 32, and only the gateelectrodes 6 a, 6 b are implanted with impurity ions. This stronglyensures the gate electrodes 6 a, 6 b to have a higher impurityconcentration than the source-and-drain regions 10 a, 10 b have.

(Modified Example)

Also in the fourth embodiment, similarly to the modified example of thefirst embodiment, conditions for the first ion implantation for formingthe source-and-drain regions or successive tilt-angled ion implantationscan properly be selected provided that the impurity concentration of thegate electrodes can be raised without increasing the impurityconcentration of the source-and-drain regions.

For example, the first ion implantation of phosphorus for forming then-type, source-and-drain region 10 a is carried out at an ionacceleration energy of 8 keV, a dose of 6×10¹⁵/cm² and an angle ofincidence of 0°, and the tilt-angled ion implantation of phosphorus iscarried out twice along the direction parallel to the gate lengthrespectively at an ion acceleration energy of 4 keV, a dose of5×10¹⁴/cm² and an angle of incidence of 450.

By the ion implantation repeated twice, as shown later in Table 1, thegate electrode 6 a will have introduced therein the impurity in anamount equivalent to that possibly attained by ion implantations at anangle of incidence of 0° (5×10¹⁴/cm²) repeated four times, in additionto a dose of 6×10¹⁵/cm² which has previously been attained, and thuswill have a total dose of phosphorus of 8×10¹⁵/cm². On the contrary,each n-type, source-and-drain region 10 a will contain the impurity onlyin an amount of 6×10¹⁵/cm² which has initially been attained, which willbe at the same level with that of general source-and-drain region.

Similarly to the above, the first ion implantation of boron for formingthe p-type, source-and-drain region 10 b is carried out at an ionacceleration energy of 4 keV, a dose of 3×10¹⁵/cm² and an angle ofincidence of 0°, and the tilt-angled ion implantation of boron iscarried out twice along the direction parallel to the gate lengthrespectively at an ion acceleration energy of 2 keV, a dose of2.5×10¹⁴/cm² and an angle of incidence of 45°.

By the ion implantation repeated twice, as shown later in Table 1, thegate electrode 6 b will have introduced therein the impurity in anamount equivalent to that possibly attained by ion implantations at anangle of incidence of 0° (2.5×10¹⁴/cm²) repeated four times, in additionto a dose of 3×10¹⁵/cm² which has previously been attained, and thuswill have a total dose of boron of 4×10¹⁵/cm². On the contrary, eachp-type, source-and-drain region 10 b will contain the impurity only inan amount of 3×10¹⁵/cm² which has initially been attained, which will beat the same level with that of general source-and-drain region.

Fifth Embodiment

FIGS. 18A through 19D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a fifth embodiment.

In the fifth embodiment, the individual process steps previously shownin FIGS. 4A through 6B are executed to thereby form the sidewalls 9 a, 9b which cover both side faces of the gate electrodes 6 a, 6 b and havinga maximum width of 80 nm or around (FIG. 18A).

Next, as shown in FIG. 18B, the resist mask 18 is formed so as to coverthe pMOS region 12, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 6×10¹⁵/cm², and an angle ofincidence of 0°, to thereby form the n-type, source-and-drain regions 10a. Phosphorus herein is also implanted into the gate electrode 6 a.

Next, the resist mask 18 is removed typically by ashing, the resist mask19 is formed so as to cover the nMOS region 11 as shown in FIG. 18C, anda p-type impurity, which is boron (B) herein, is introduced by ionimplantation into the pMOS region 12 at an ion acceleration energy of 4keV, a dose of 3×10¹⁵/cm² and an angle of incidence of 0°, to therebyform the p-type, source-and-drain regions 10 b. Boron herein is alsoimplanted into the gate electrode 6 b.

Next, the resist mask 19 is removed typically by ashing, and thesidewalls 9 a, 9 b are dry-etched (over-etched) to thereby allow theupper portion of both side faces of the gate electrodes 6 a, 6 b toexpose as much as 50 nm or around as shown in FIG. 18D. The gateelectrodes 6 a, 6 b herein are remained so as to expose an areaextending from the top surface thereof to the upper portion of both sidefaces thereof, and the sidewalls 9 a, 9 b are adjusted so as to have aheight of 50 nm or around.

Considering now that the gate electrodes 6 a, 6 b are subjected totilt-angled ion implantation described later, the more the sidewalls 9a, 9 b are etched, the more the gate electrodes 6 a, 6 b will have animpurity incorporated therein. Too much amount of etching of thesidewalls 9 a, 9 b may, however, result in excessive diffusion of theincorporated impurity in the source-and-drain regions 10 a, 10 b towardsthe channel, or may raise a risk of short-circuiting between suicides,which are formed later on the source-and-drain regions 10 a, 10 b and onthe gate electrodes 6 a, 6 b. Thus there is an appropriate range for theamount of etching of the sidewalls 9 a, 9 b, and 50 nm is one exemplaryamount falls within such range.

To prevent the STI-type element isolation structure 2 from being etchedtogether with the sidewalls 9 a, 9 b, it is preferable to use differentmaterials to form the sidewalls 9 a, 9 b and STI-type element isolationstructure 2 so that the sidewalls 9 a, 9 b will have a higher etchratethan that of the element isolation structure 2. One preferable exampleis such that using a plasma oxide film formed in an HDP (high densityplasma) apparatus for the STI-type element isolation structure 2 andusing an oxide film formed using TEOS (tetraethoxysilane) for thesidewalls 9 a, 9 b.

Next, as shown in FIG. 19A, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide and both side faces of 50 nm high exposed from thesidewall 9 a).

More specifically, a resist mask 33 is formed so as to cover the pMOSregion 12, which mask 33 having an opening 33 a formed in a size capableof protecting the n-type, source-and-drain regions 10 a from thetilt-angled ion implantation. The resist mask 33 herein is approx. 120nm high, and the opening 33 a has an edge 120 nm away from the edge ofthe gate electrode 6 a. In alignment of a reticle for forming theopening 33 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. An n-type impurity, which isphosphorus (P) herein, is implanted into the nMOS region 11 at an ionacceleration energy of 4 keV, a dose of 5×10¹⁴/cm², and an angle ofincidence of 45°. The implantation is repeated four times fromdirections differing from each other (four different directions inclinedby 45° away from the direction of gate length). The ion implantationrepeated four times is shown in a schematic plan view in FIG. 20.

A single ion implantation according to the above conditions results inintroduction of the impurity over the area extending from the topsurface to the upper portion of one side face of the gate electrode 6 ain an amount equivalent to that possibly attained by ion implantationsat an angle of incidence of 0° repeated twice. On the other hand, a pairof n-type, source-and-drain regions 10 a are protected by the resistmask 33 against the ion implantation, and are thus prevented from beingimplanted with the impurity.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 a will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (5×10¹⁴/cm²) repeated eighttimes, in addition to a dose of 6×10¹⁵/cm² which has previously beenattained, and thus will have a total dose of phosphorus of 1×10¹⁶/cm².On the contrary, each n-type, source-and-drain region 10 a will containthe impurity only in an amount of 6×10¹⁵/cm² which has initially beenattained, which will be at the same level with that of generalsource-and-drain region.

In the aforementioned process for forming the n-type, source-and-drainregion 10 a, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 8 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 4 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 a, to prevent the impurity frompenetrating the sidewall 10 a and gate electrode 6 a and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the n-type, source-and-drain region 10 a from diffusing toward thechannel.

Next, as shown in FIG. 19B, a p-type impurity is implanted into the pMOSregion 12 to thereby introduce the impurity to the exposed surface ofthe gate electrode 6 b (the top surface of 50 nm wide and both sidefaces of 50 nm high exposed from the sidewall 9 b).

More specifically, the resist mask 33 is removed typically by ashing,and a resist mask 34 is formed so as to cover the nMOS region 11, whichmask 34 having an opening 34 a formed in a size capable of protectingthe p-type, source-and-drain regions 10 b from the tilt-angled ionimplantation. The resist mask 34 herein is approx. 120 nm high, and theopening 34 a has an edge 120 nm away from the edge of the gate electrode6 b. In alignment of a reticle for forming the opening 31 a byphotolithography, employing the gate electrode as an alignment mark, inplace of a mark formed in the STI process, can successfully reducemis-alignment. A p-type impurity, which is boron (B) herein, isimplanted into the pMOS region 12 at an ion acceleration energy of 2keV, a dose of 2.5×10¹⁴/cm², and an angle of incidence of 45°. Theimplantation is repeated four times from directions differing from eachother (four different directions inclined by 45° away from the directionof gate length).

A single ion implantation according to the above conditions results inintroduction of the impurity over the area extending from the topsurface to the upper portion of one side face of the gate electrode 6 bin an amount equivalent to that possibly attained by ion implantationsat an angle of incidence of 0° repeated twice. On the other hand, a pairof p-type, source-and-drain regions 10 b are protected by the resistmask 34 against the ion implantation, and are thus prevented from beingimplanted with the impurity.

By the aforementioned ion implantation repeated four times, as shownlater in Table 1, the gate electrode 6 b will have introduced thereinthe impurity in an amount equivalent to that possibly attained by ionimplantations at an angle of incidence of 0° (2.5×10¹⁴/cm²) repeatedeight times, in addition to a dose of 3×10¹⁵/cm² which has previouslybeen attained, and thus will have a total dose of boron of 5×10¹⁵/cm².On the contrary, each p-type, source-and-drain region 10 b will containthe impurity only in an amount of 3×10¹⁵/cm² which has initially beenattained, which will be at the same level with that of generalsource-and-drain region.

In the aforementioned process for forming the p-type, source-and-drainregion 10 b, the first ion implantation (at an angle of incidence of 0°)was carried out at an ion acceleration energy of 4 keV, whereas thesuccessive tilt-angled ion implantation was carried at an ionacceleration energy reduced to as low as 2 keV. The energy was thusreduced because it was necessary to prevent the impurity from laterallypenetrating the gate electrode 6 b, to prevent the impurity frompenetrating the sidewall 10 b and gate electrode 6 b and intruding intothe semiconductor substrate 1, and to prevent the impurity implantedinto the n-type, source-and-drain region 10 b from diffusing toward thechannel.

Next, the resist mask 34 is removed typically by ashing, and, as shownin FIG. 19C, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,030° C. for one second to thereby restoreit from damage caused by ion implantation into the gate electrodes 6 a,6 b and source-and-drain regions 10 a, 10 b, and to thereby activate theimpurities.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 19D.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the fifth embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b by formingthe sidewalls 9 a, 9 a so as to expose the upper portion of the gateelectrodes 6 a, 6 b, and by carrying out the ion implantation from fourinclined directions at an angle of incidence of 45°. In the fifthembodiment, the impurity concentration of the gate electrodes 6 a, 6 bbecomes higher than that of the source-and-drain regions 10 a, 10 b byapprox. 66%, where the impurity concentration of the gate electrodes 6a, 6 b can be raised while keeping the general impurity concentration ofthe source-and-drain regions 10 a, 10 b unchanged. The fifth embodimentis thus to provide a highly-reliable CMOS transistor having an improvedgate capacitance and short-channel resistance without anticipatingfluctuation in the threshold voltage due to variation in shape of thegate electrode.

In addition, the source-and-drain regions 10 a, 10 b are successfullyprevented from being implanted with the impurities by virtue of theresist masks 33, 34, and only the gate electrodes 6 a, 6 b are implantedwith impurity ions. This strongly ensures the gate electrodes 6 a, 6 bto have a higher impurity concentration than the source-and-drainregions 10 a, 10 b have.

Short-circuiting between the silicides formed on the source-and-drainregions 10 a, 10 b and the silicides formed on the gate electrodes 6 a,6 b can be prevented by combining the fifth embodiment and secondembodiment. This desirably increases the amount of etching of thesidewalls 9 a, 9 b than that in the fifth embodiment, and makes itpossible to further increase the dose of impurities incorporated intothe gate electrodes 6 a, 6 b. It is even allowable to completely removethe sidewalls 9 a, 9 b by over-etching, because the introduction ofimpurities into the source-and-drain regions 10 a, 10 b can be preventedby the resist masks 33, 34 even in the absence of the sidewalls 9 a, 9b.

Sixth Embodiment

FIGS. 21A through 23D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a sixth embodiment.

In the sixth embodiment, the individual process steps previously shownin FIGS. 4A through 5C are executed similarly to as described in thefirst embodiment, to thereby pattern the gate electrodes 6 a, 6 b (FIG.21A).

Next, as shown in FIG. 21B, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide).

More specifically, a resist mask 35 is formed so as to cover the pMOSregion 12, which mask 35 having an opening 35 a formed in a size capableof protecting the n-type, source-and-drain regions 10 a from thetilt-angled ion implantation. The resist mask 35 herein is approx. 120nm high, and the opening 35 a has an edge 80 nm away from the edge ofthe gate electrode 6 a. In alignment of a reticle for forming theopening 35 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. An n-type impurity, which isphosphorus (P) herein, is implanted into the nMOS region 11 at an ionacceleration energy of 4 keV, a dose of 5×10¹⁴/cm², and an angle ofincidence of 45°. The implantation is repeated four times fromdirections differing from each other (four different directions inclinedby 45° away from the direction of the gate electrode 6 b. In alignmentof a reticle for forming the opening 36 a by photolithography, employingthe gate electrode as an alignment mark, in place of a mark formed inthe STI process, can successfully reduce mis-alignment. A p-typeimpurity, which is boron (B) herein, is implanted into the pMOS region12 at an ion acceleration energy of 2 keV, a dose of 2.5×10¹⁴/cm², andan angle of incidence of 45°. The implantation is repeated four timesfrom directions differing from each other (four different directionsinclined by 45° away from the direction of gate length).

A single ion implantation according to the above conditions results inintroduction of the impurity over the area extending from the topsurface to the upper portion of one side face of the gate electrode 6 bin an amount equivalent to that possibly attained by ion implantationsat an angle of incidence of 0° repeated twice. On the other hand, a pairof p-type, source-and-drain regions 10 b are protected by the resistmask 36 against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, the resist mask 36 is removed typically by ashing, the resist mask16 is formed so as to cover the pMOS region 12 as shown in FIG. 21D, andan n-type impurity, which is arsenic (As) herein, is introduced byvertical ion implantation into the nMOS region 11 at an ion accelerationenergy of 5 keV and a dose of 6×10¹⁴/cm²; and a p-type impurity, whichis boron (B) herein, is also introduced by ion implantation at an ionacceleration energy of 10 keV, a dose of 8×10¹²/cm² and at an angle ofincidence of 30° from four directions to thereby form n-type extensionlayers 7 a and p-type pocket layers 8 a, respectively.

Next, the resist mask 16 is removed typically by ashing, the resist mask17 is formed so as to cover the nMOS region 11 as shown in FIG. 22A, anda p-type impurity, which is boron (B) herein, is introduced by verticalion implantation into the pMOS region 12 at an ion acceleration energyof 0.5 keV and a dose of 6×10¹⁴/cm²; and an n-type impurity, which isarsenic (As) herein, is also introduced by ion implantation at an ionacceleration energy of 50 keV, a dose of 6×10¹²/cm² and at an angle ofincidence of 30° from four directions to thereby form p-type extensionlayers 7 b and n-type pocket layers 8 b, respectively.

It is to be noted now that the individual process steps shown in FIGS.21B through 22A can be executed in an arbitrary order.

Next, the resist mask 17 is removed typically by ashing, and, as shownin FIG. 22B, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,000° C. for one second to thereby restoreit from damage caused by the ion implantation into the extension layers7 a, 7 b and pocket layers 8 a, 8 b.

Next, a silicon oxide film (not shown) is deposited on the entiresurface by the CVD process, and the film is then anisotropically etchedback so as to allow the film to remain only on both side faces of thegate electrodes 6 a, 6 b, to thereby form sidewalls 20 a, 20 b having amaximum width of 80 nm or around, as shown in FIG. 22C.

Next, a resist mask 18 is formed so as to cover the pMOS region 12 asshown in FIG. 22D, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 6×10¹⁵/cm², and an angle ofincidence of 0° (that is, normal to the surface of the substrate), tothereby form the n-type, source-and-drain regions 10 a. Phosphorusherein is also implanted into the gate electrode 6 a.

In this case, the gate electrode 6 a is subjected to four times of theaforementioned tilt-angled ion implantation and a single ionimplantation at an angle of incidence of 0°, which results inintroduction of the impurity in an amount equivalent to eight times of5×10¹⁴/cm² plus 6×10¹⁵/cm², total 1×10¹⁶/cm² of phosphorus. On thecontrary, each n-type, source-and-drain region 10 a will have introducedtherein the impurity only in an amount of 6×10¹⁵/cm², into the gateelectrodes 6 a, 6 b and source-and-drain regions 10 a, 10 b, and tothereby activate the impurities.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form COSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 23C.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processesas shown in FIG. 23D.

As has been described in the above, the sixth embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b bycarrying out the ion implantation from four inclined directions at anangle of incidence of 45°. In the sixth embodiment, the impurityconcentration of the gate electrodes 6 a, 6 b becomes higher than thatof the source-and-drain regions 10 a, 10 b by approx. 66%, where theimpurity concentration of the gate electrodes 6 a, 6 b can be raisedwhile keeping the general impurity concentration of the source-and-drainregions 10 a, 10 b unchanged. The sixth embodiment is thus to provide ahighly-reliable CMOS transistor having an improved gate capacitance andshort-channel resistance without anticipating fluctuation in thethreshold voltage due to variation in shape of the gate electrode.

Moreover, in the tilt-angled ion implantation, the source-and-drainregions 10 a, 10 b are successfully prevented from being implanted withthe impurities by virtue of the resist masks 35, 36, and only the gateelectrodes 6 a, 6 b are implanted with impurity ions. This stronglyensures the gate electrodes 6 a, 6 b to have a higher impurityconcentration than the source-and-drain regions 10 a, 10 b have.

The sixth embodiment is also advantageous in reducing the productioncost of CMOS transistor, since a process step of thinning the sidewalls20 a, 20 b by over-etching is omissible, although the amounts of dose ofimpurities in the source-and-drain regions 10 a, 10 b and gateelectrodes 6 a, 6 b are attainable at the same level with those in thefifth embodiment.

Seventh Embodiment

FIGS. 25A through 27D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a seventh embodiment.

directions inclined by 45° away from the direction of gate length).

Since the top surface and the upper portion of one side face of the gateelectrode 6 a herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 a in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice. On the other hand, a pair of n-type,source-and-drain regions 10 a are protected by the resist mask 37against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, as shown in FIG. 25B, in the presence of the resist mask 37remained unremoved, an n-type impurity, which is arsenic (As) herein, isvertically implanted into the nMOS region 11 at an ion accelerationenergy of 5 keV and a dose of 6×10¹⁴/cm²; and a p-type impurity, whichis boron (B) herein, is also introduced by ion implantation at an ionacceleration energy of 10 keV, a dose of 8×10¹²/cm² and at an angle ofincidence of 15° from four directions to thereby form n-type extensionlayers 7 a and p-type pocket layers 8 a, respectively.

Next, as shown in FIG. 25C, a p-type impurity is implanted along adirection inclined into the pMOS region 12 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 b (the topsurface of 50 nm wide).

More specifically, the resist mask 37 is removed typically by ashing,and a resist mask 38 is formed so as to cover the nMOS region 11, whichmask 38 having an opening 38 a formed in a size capable of protectingthe p-type, source-and-drain regions 10 b from the tilt-angled ionimplantation. The resist mask 38 herein is approx. 120 nm high, and theopening 38 a has an edge 80 nm away from the edge of the gate electrode6 b. In alignment of a reticle for forming the opening 38 a byphotolithography, employing the gate electrode as an alignment mark, inplace of a mark formed in the STI process, can successfully reducemis-alignment. A p-type impurity, which is boron (B) herein, isimplanted into the pMOS region 12 at an ion acceleration energy of 2keV, a dose of 2.5×10¹⁴/cm², and an angle of incidence of 45°. Theimplantation is repeated four times from directions differing from eachother (four different directions inclined by 45° away from the directionof gate length).

A single ion implantation according to the above conditions results inintroduction of the impurity over the area extending from the topsurface to the upper portion of one side face of the gate electrode 6 bin an amount equivalent to that possibly attained by ion implantationsat an angle of incidence of 0° repeated twice. On the other hand, a pairof p-type, source-and-drain regions 10 b are protected by the resistmask 38 against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, as shown in FIG. 25D, in the presence of the resist mask 38remained unremoved, a p-type impurity, which is boron (B) herein, isvertically implanted into the pMOS region 12 at an ion accelerationenergy of 0.5 keV and a dose of 6×10¹⁴/cm²; and an n-type impurity,which is arsenic (As) herein, is also introduced by ion implantation atan ion acceleration energy of 50 keV, a dose of 6×10¹²/cm² and at anangle of incidence of 15° from four directions to thereby form p-typeextension layers 7 b and n-type pocket layers 8 b, respectively.

Next, the resist mask 38 is removed typically by ashing, and, as shownin FIG. 26A, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,000° C. for one second to thereby restoreit from damage caused by the ion implantation into the extension layers7 a, 7 b and pocket layers 8 a, 8 b.

Next, a silicon oxide film (not shown) is deposited on the entiresurface by the CVD process, and the film is then anisotropically etchedback so as to allow the film to remain only on both side faces of thegate electrodes 6 a, 6 b, to thereby form sidewalls 9 a, 9 b having amaximum width of 80 nm or around, as shown in FIG. 26B.

Next, a resist mask 18 is formed so as to cover the pMOS region 12 asshown in FIG. 26C, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 6×10¹⁵/cm², and an angle ofincidence of 0° (that is, normal to the surface of the substrate), tothereby form the n-type, source-and-drain regions 10 a. Phosphorusherein is also implanted into the gate electrode 6 a.

In this case, the gate electrode 6 a is subjected to four times of theaforementioned tilt-angled ion implantation and a single ionimplantation at an angle of incidence of 0°, which results inintroduction of the impurity in an amount equivalent to eight times of5×10¹⁴/cm² plus 6×10¹⁵/cm², total 1×10¹⁶/cm² of phosphorus. On thecontrary, each n-type, source-and-drain region 10 a will have introducedtherein the impurity only in an amount of 6×10¹⁵/cm², which will be atthe same level with that of general source-and-drain region.

Next, a resist mask 18 is removed typically by ashing, and the resistmask 19 is formed so as to cover the nMOS region 11 as shown in FIG.26D, and a p-type impurity, which is boron (B) herein, is introduced byion implantation into the pMOS region 12 at an ion acceleration energyof 4 keV, a dose of 3×10¹⁵/cm², and an angle of incidence of 0°, tothereby form the p-type, source-and-drain regions 10 b. Boron herein isalso implanted into the gate electrode 6 b.

In this case, the gate electrode 6 b is subjected to four times of theaforementioned tilt-angled ion implantation and a single ionimplantation at an angle of incidence of 0°, which results inintroduction of the impurity in an amount equivalent to eight times of2.5×10¹⁴/cm² plus 3×10¹⁵/cm², total 5×10¹⁵/cm² of boron. On thecontrary, each p-type, source-and-drain region 10 b will have introducedtherein the impurity only in an amount of 3×10¹⁵/cm², which will be atthe same level with that of general source-and-drain region.

Next, the resist mask 19 is removed typically by ashing, and, as shownin FIG. 27A, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,030° C. for one second to thereby restoreit from damage caused by ion implantation into the gate electrodes 6 a,6 b and source-and-drain regions 10 a, 10 b, and to thereby activate theimpurities.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 27B.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processesas shown in FIG. 27C.

As has been described in the above, the seventh embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b bycarrying out the ion implantation from four inclined directions at anangle of incidence of 45°. In the seventh embodiment, the impurityconcentration of the gate electrodes 6 a, 6 b becomes higher than thatof the source-and-drain regions 10 a, 10 b by approx. 66%, where theimpurity concentration of the gate electrodes 6 a, 6 b can be raisedwhile keeping the general impurity concentration of the source-and-drainregions 10 a, 10 b unchanged. The seventh embodiment is thus to providea highly-reliable CMOS transistor having an improved gate capacitanceand short-channel resistance without anticipating fluctuation in thethreshold voltage due to variation in shape of the gate electrode.

Moreover, in the tilt-angled ion implantation, the source-and-drainregions 10 a, 10 b are successfully prevented from being implanted withthe impurities by virtue of the resist masks 37, 38, and only the gateelectrodes 6 a, 6 b are implanted with impurity ions. This stronglyensures the gate electrodes 6 a, 6 b to have a higher impurityconcentration than the source-and-drain regions 10 a, 10 b have.

The seventh embodiment is also advantageous in further reducing theproduction cost of CMOS transistor, since a process step of thinning thesidewalls 20 a, 20 b by over-etching is omissible, and since a processstep of photolithography for forming the extension layers 7 a, 7 b andpocket layers 8 a, 8 b is omissible, although the amounts of dose ofimpurities in the source-and-drain regions 10 a, 10 b and gateelectrodes 6 a, 6 b are attainable at the same level with those in thefifth embodiment.

(Modified Example)

A modified example of the seventh embodiment will be described.

FIGS. 28A through 29C are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a modified example of the seventh embodiment.

In this modified example, similarly to as previously shown in FIG. 25B,the gate electrode 6 a is subjected to the tilt-angled ion implantationin the presence of the resist mask 37 (FIG. 28A).

Next, as shown in FIG. 28B, the resist mask 37 is trimmed so that theopening 37 a is widened to have an edge recessed by 100 nm from the edgeof the gate electrode 6 a.

In this status, as shown in FIG. 28C, an n-type impurity, which isarsenic (As) herein, is vertically implanted into the nMOS region 11 atan ion acceleration energy of 5 keV and a dose of 6×10¹⁴/cm²; and ap-type impurity, which is boron (B) herein, is also introduced by ionimplantation at an ion acceleration energy of 10 keV, a dose of8×10¹²/cm² and at an angle of incidence of 30° from four directions tothereby form the n-type extension layers 7 a and p-type pocket layers 8a, respectively.

Next, the resist mask 37 is removed typically by ashing, and thensimilarly to as previously shown in FIG. 25C, the gate electrode 6 b issubjected to the tilt-angled ion implantation in the presence of theresist mask 38 (FIG. 29A).

Next, as shown in FIG. 29B, the resist mask 38 is trimmed so that theopening 38 a is widened to have an edge recessed by 100 nm from the edgeof the gate electrode 6 b.

In this status, a p-type impurity, which is boron (B) herein, isvertically implanted into the PMOS region 12 at an ion accelerationenergy of 0.5 keV and a dose of 6×10¹⁴/cm²; and an n-type impurity,which is arsenic (As) herein, is also introduced by ion implantation atan ion acceleration energy of 50 keV, a dose of 6×10¹²/cm² and at anangle of incidence of 30° from four directions to thereby form thep-type extension layers 7 b and n-type pocket layers 8 b, respectively.

The resist mask 38 is then removed typically by ashing, and a CMOStransistor is completed after executing various process steps similarlyto those in the seventh embodiment as shown in FIGS. 26A to 27C.

In addition to various effects obtainable from the seventh embodiment,this modified example makes it possible to form the extension layers 7a, 7 b and pocket layers 8 a, 8 b expanded to desired dimensions at ahigh degree of freedom by trimming the resist masks 37, 38, withoutlimiting dimensions of the extension layers 7 a, 7 b and pocket layers 8a, 8 b in view of preventing the tilt-angled ion implantation.

Eighth Embodiment

FIGS. 30A through 32D are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a eighth embodiment.

In the eighth embodiment, the individual process steps previously shownin FIGS. 4A through 5C are executed similarly to as described in thefirst embodiment, to thereby pattern the gate electrodes 6 a, 6 b (FIG.30A).

Next, as shown in FIG. 30B, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide).

More specifically, the resist mask 35 is formed so as to cover the PMOSregion 12, which mask 35 having the opening 35 a formed in a sizecapable of protecting the n-type, source-and-drain regions 10 a from thetilt-angled ion implantation. The resist mask 35 herein is approx. 120nm high, and the opening 35 a has an edge 80 nm away from the edge ofthe gate electrode 6 a. In alignment of a reticle for forming theopening 35 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. An n-type impurity, which isphosphorus (P) herein, is implanted into the nMOS region 11 at an ionacceleration energy of 4 keV, a dose of 5×10¹⁴/cm², and an angle ofincidence of 45°. The implantation is repeated four times fromdirections differing from each other (four different directions inclinedby 45° away from the direction of gate length).

Since the top surface and the upper portion of one side face of the gateelectrode 6 a herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 a in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice. On the other hand, a pair of n-type,source-and-drain regions 10 a are protected by the resist mask 35against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, as shown in FIG. 30C, a p-type impurity is implanted along adirection inclined into the pMOS region 12 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 b (the topsurface of 50 nm wide).

More specifically, the resist mask 35 is removed typically by ashing,and the resist mask 36 is formed so as to cover the nMOS region 11,which mask 36 having the opening 36 a formed in a size capable ofprotecting the p-type, source-and-drain regions 10 b from thetilt-angled ion implantation. The resist mask 36 herein is approx. 120nm high, and the opening 36 a has an edge 80 nm away from the edge ofthe gate electrode 6 b. In alignment of a reticle for forming theopening 36 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. A p-type impurity, which is boron (B)herein, is implanted into the pMOS region 12 at an ion accelerationenergy of 2 keV, a dose of 2.5×10¹⁴/cm², and an angle of incidence of45°. The implantation is repeated four times from directions differingfrom each other (four different directions inclined by 45° away from thedirection of gate length).

A single ion implantation according to the above conditions results inintroduction of the impurity over the area extending from the topsurface to the upper portion of one side face of the gate electrode 6 bin an amount equivalent to that possibly attained by ion implantationsat an angle of incidence of 0° repeated twice. On the other hand, a pairof p-type, source-and-drain regions 10 b are protected by the resistmask 36 against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, the resist mask 36 is removed typically by ashing, and, as shownin FIG. 30D, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,050° C. for 1 second to therebythoroughly diffuse the impurities incorporated into the gate electrodes6 a, 6 b.

Next, the resist mask 16 is formed so as to cover the pMOS region 12 asshown in FIG. 31A, and an n-type impurity, which is arsenic (As) herein,is introduced by vertical ion implantation into the nMOS region 11 at anion acceleration energy of 5 keV and a dose of 6×10¹⁴/cm²; and a p-typeimpurity, which is boron (B) herein, is also introduced by ionimplantation at an ion acceleration energy of 10 keV, a dose of8×10¹²/cm² and at an angle of incidence of 30° from four directions tothereby form the n-type extension layers 7 a and p-type pocket layers 8a, respectively.

Next, the resist mask 16 is removed typically by ashing, the resist mask17 is formed so as to cover the nMOS region 11 as shown in FIG. 31B, anda p-type impurity, which is boron (B) herein, is introduced by verticalion implantation into the pMOS region 12 at an ion acceleration energyof 0.5 keV and a dose of 6×10¹⁴/cm²; and an n-type impurity, which isarsenic (As) herein, is also introduced by ion implantation at an ionacceleration energy of 50 keV, a dose of 6×10¹²/cm² and at an angle ofincidence of 30° from four directions to thereby form the p-typeextension layers 7 b and n-type pocket layers 8 b, respectively.

Next, the resist mask 17 is removed typically by ashing, and, as shownin FIG. 31C, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,000° C. for one second to thereby restoreit from damage caused by the ion implantation into the extension layers7 a, 7 b and pocket layers 8 a, 8 b.

Next, a silicon oxide film (not shown) is deposited on the entiresurface by the CVD process, and the film is then anisotropically etchedback so as to allow the film to remain only on both side faces of thegate electrodes 6 a, 6 b, to thereby form sidewalls 9 a, 9 b having amaximum width of 80 nm or around, as shown in FIG. 31D.

Next, a resist mask 18 is formed so as to cover the pMOS region 12 asshown in FIG. 32A, and an n-type impurity, which is phosphorus (P)herein, is introduced by ion implantation into the nMOS region 11 at anion acceleration energy of 8 keV, a dose of 6×10¹⁵/cm², and an angle ofincidence of 0° (that is, normal to the surface of the substrate), tothereby form the n-type, source-and-drain regions 10 a. Phosphorusherein is also implanted into the gate electrode 6 a.

In this case, the gate electrode 6 a is subjected to four times of theaforementioned tilt-angled ion implantation and a single ionimplantation at an angle of incidence of 0°, which results inintroduction of the impurity in an amount equivalent to eight times of5×10¹⁴/cm² plus 6×10¹⁵/cm², total 1×10¹⁶/cm² of phosphorus. On thecontrary, each n-type, source-and-drain region 10 a will have introducedtherein the impurity only in an amount of 6×10¹⁵/cm², which will be atthe same level with that of general source-and-drain region.

Next, a resist mask 18 is removed typically by ashing, and the resistmask 19 is formed so as to cover the nMOS region 11 as shown in FIG.32B, and a p-type impurity, which is boron (B) herein, is introduced byion implantation into the pMOS region 12 at an ion acceleration energyof 4 keV, a dose of 3×10¹⁵/cm², and an angle of incidence of 0°, tothereby form the p-type, source-and-drain regions 10 b. Boron herein isalso implanted into the gate electrode 6 b.

In this case, the gate electrode 6 b is subjected to four times of theaforementioned tilt-angled ion implantation and a single ionimplantation at an angle of incidence of 0°, which results inintroduction of the impurity in an amount equivalent to eight times of2.5×10¹⁴/cm² plus 3×10¹⁵/cm², total 5×10¹⁵/cm² of boron. On thecontrary, each p-type, source-and-drain region 10 b will have introducedtherein the impurity only in an amount of 3×10¹⁵/cm², which will be atthe same level with that of general source-and-drain region.

Next, the resist mask 19 is removed typically by ashing, and, as shownin FIG. 32C, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,020° C. for one second to thereby restoreit from damage caused by ion implantation into the gate electrodes 6 a,6 b and source-and-drain regions 10 a, 10 b, and to thereby activate theimpurities. As described in the above, annealing temperature herein inthe eighth embodiment can be reduced from 1,030° C. to 1,020° C. sincethe impurities introduced into the gate electrode 6 a, 6 b have alreadybeen activated in the process step shown in FIG. 30D, which isadvantageous in further suppressing diffusion of the impurities in theextension layers 7 a, 7 b and pocket layers 8 a, 8 b, and thussuppressing the short-channel effect.

Next, a silicide-forming metal, which is cobalt (Co) herein, isdeposited over the entire surface, annealed so as to proceedsilicidation, and unreacted Co is removed, to thereby form CoSi₂ layers23 on the exposed surface of the gate electrodes 6 a, 6 b and on thesurface of the source-and-drain region 10 a, 10 b as shown in FIG. 32D.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the eighth embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b bycarrying out the ion implantation from four inclined directions at anangle of incidence of 45°. In the eighth embodiment, the impurityconcentration of the gate electrodes 6 a, 6 b becomes higher than thatof the source-and-drain regions 10 a, 10 b by approx. 66%, where theimpurity concentration of the gate electrodes 6 a, 6 b can be raisedwhile keeping the general impurity concentration of the source-and-drainregions 10 a, 10 b unchanged. The eighth embodiment is thus to provide ahighly-reliable CMOS transistor having an improved gate capacitance andshort-channel resistance without anticipating fluctuation in thethreshold voltage due to variation in shape of the gate electrode.

Moreover, in the tilt-angled ion implantation, the source-and-drainregions 10 a, 10 b are successfully prevented from being implanted withthe impurities by virtue of the resist masks 35, 36, and only the gateelectrodes 6 a, 6 b are implanted with impurity ions. This stronglyensures the gate electrodes 6 a, 6 b to have a higher impurityconcentration than the source-and-drain regions 10 a, 10 b have.

The eighth embodiment is also advantageous in reducing the productioncost of CMOS transistor, since a process step of thinning the sidewalls20 a, 20 b by over-etching is omissible, although the amounts of dose ofimpurities in the source-and-drain regions 10 a, 10 b and gateelectrodes 6 a, 6 b are attainable at the same level with those in thefifth embodiment. Still another advantage resides in that the impurityconcentration of the gate electrodes 6 a, 6 b can be raised in thevicinity of the gate insulating film 5, since the semiconductorsubstrate 1 is once annealed immediately after the gate electrodes 6 a,6 b are subjected to the tilt-angled ion implantation.

Ninth Embodiment

FIGS. 33A through 34C are schematic sectional views sequentially showingmajor process steps of a method of fabricating a CMOS transistoraccording to a ninth embodiment.

In the ninth embodiment, the individual process steps previously shownin FIGS. 4A through 5C are executed similarly to as described in thefirst embodiment, to thereby pattern the gate electrodes 6 a, 6 b (FIG.33A).

Next, as shown in FIG. 33B, an n-type impurity is implanted along adirection inclined into the nMOS region 11 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 a (the topsurface of 50 nm wide).

More specifically, the resist mask 35 is formed so as to cover the pMOSregion 12, which mask 35 having the opening 35 a formed in a sizecapable of protecting the n-type, source-and-drain regions 10 a from thetilt-angled ion implantation. The resist mask 35 herein is approx. 120nm high, and the opening 35 a has an edge 80 nm away from the edge ofthe gate electrode 6 a. In alignment of a reticle for forming theopening 35 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. An n-type impurity, which isphosphorus (P) herein, is implanted into the nMOS region 11 at an ionacceleration energy of 4 keV, a dose of 5×10¹⁴/cm² and an angle ofincidence of 45°. The implantation is repeated four times fromdirections differing from each other (four different directions inclinedby 45° away from the direction of gate length).

Since the top surface and the upper portion of one side face of the gateelectrode 6 a herein have almost equivalent exposed areas, a single ionimplantation according to the above conditions results in introductionof the impurity over the area extending from the top surface to theupper portion of one side face of the gate electrode 6 a in an amountequivalent to that possibly attained by ion implantations at an angle ofincidence of 0° repeated twice. On the other hand, a pair of n-type,source-and-drain regions 10 a are protected by the resist mask 35against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, as shown in FIG. 33C, a p-type impurity is implanted along adirection inclined into the pMOS region 12 to thereby introduce theimpurity to the exposed surface of the gate electrode 6 b (the topsurface of 50 nm wide).

More specifically, the resist mask 35 is removed typically by ashing,and the resist mask 36 is formed so as to cover the nMOS region 11,which mask 36 having the opening 36 a formed in a size capable ofprotecting the p-type, source-and-drain regions 10 b from thetilt-angled ion implantation. The resist mask 36 herein is approx. 120nm high, and the opening 36 a has an edge 80 nm away from the edge ofthe gate electrode 6 b. In alignment of a reticle for forming theopening 36 a by photolithography, employing the gate electrode as analignment mark, in place of a mark formed in the STI process, cansuccessfully reduce mis-alignment. A p-type impurity, which is boron (B)herein, is implanted into the PMOS region 12 at an ion accelerationenergy of 2 keV, a dose of 2.5×10¹⁴/cm², and an angle of incidence of45°. The implantation is repeated four times from directions differingfrom each other (four different directions inclined by 45° away from thedirection of gate length).

A single ion implantation according to the above conditions results inintroduction of the impurity over the area extending from the topsurface to the upper portion of one side face of the gate electrode 6 bin an amount equivalent to that possibly attained by ion implantationsat an angle of incidence of 0° repeated twice. On the other hand, a pairof p-type, source-and-drain regions 10 b are protected by the resistmask 36 against the ion implantation, and are thus prevented from beingimplanted with the impurity.

Next, the resist mask 36 is removed typically by ashing, and, as shownin FIG. 33D, a resist mask 41 is formed so as to cover the pMOS region12, and an n-type impurity, which is phosphorus (P) herein, isintroduced by ion implantation into the nMOS region 11 at an ionacceleration energy of 8 keV and a dose of 6×10¹⁵/cm², to thereby formn-type, source-and-drain regions 43 a.

Next, the resist mask 41 is removed typically by ashing, and, as shownin FIG. 34A, a resist mask 42 is formed so as to cover the nMOS region11, and an p-type impurity, which is boron (B) herein, is introduced byion implantation into the pMOS region 12 at an ion acceleration energyof 4 keV and a dose of 3×10¹⁵/cm², to thereby form p-type,source-and-drain regions 43 b.

Next, the resist mask 42 is removed typically by ashing, and, as shownin FIG. 34B, the semiconductor substrate 1 is then annealed by RTA(rapid thermal annealing) at 1,030° C. for 1 second to therebythoroughly activate the impurities incorporated into the gate electrodes6 a, 6 b and the source-and-drain regions 43 a, 43 b.

An interlayer insulating film 24 is deposited over the entire surface,wirings 26 are formed so as to make contact through contact holes 25,and a CMOS transistor is completed after some additional post-processes.

As has been described in the above, the ninth embodiment is successfulin controlling the impurity concentration of the gate electrodes 6 a, 6b higher than that of the source-and-drain regions 10 a, 10 b bycarrying out the ion implantation from four inclined directions at anangle of incidence of 45°. In the ninth embodiment, the impurityconcentration of the gate electrodes 6 a, 6 b can be raised withoutaltering the general impurity concentration of the source-and-drainregions 10 a, 10 b. The ninth embodiment is thus to provide ahighly-reliable CMOS transistor having an improved gate capacitance andshort-channel resistance without anticipating fluctuation in thethreshold voltage due to variation in shape of the gate electrode, by aless number of process steps.

Moreover, in the tilt-angled ion implantation, the source-and-drainregions 10 a, 10 b are successfully prevented from being implanted withthe impurities by virtue of the resist masks 35, 36, and only the gateelectrodes 6 a, 6 b are implanted with impurity ions. This stronglyensures the gate electrodes 6 a, 6 b to have a higher impurityconcentration than the source-and-drain regions 10 a, 10 b have.

The amount of dose in the gate electrodes and source-and-drain regionsaccording to the first through ninth embodiments are now listed in Table1 below. TABLE 1 nMOS pMOS Dose in gate Dose in S/D Dose in gate Dose inS/D Prior art   6 × 10¹⁵ 6 × 10¹⁵   3 × 10¹⁵ 3 × 10¹⁵ (1/cm²) 1st 7.5 ×10¹⁵ (1a) 6 × 10¹⁵ (1b) 3.75 × 10¹⁵ 3 × 10¹⁵ (1d) embodiment (1c)Modified 7.5 × 10¹⁵ (2a) 6 × 10¹⁵ (2b) 3.75 × 10¹⁵ 3 × 10¹⁵ (2d) example(2c) 3rd   9 × 10¹⁵ (3a) 6 × 10¹⁵ (3b)  4.5 × 10¹⁵ 3 × 10¹⁵ (3d)embodiment (3c) 4th   8 × 10¹⁵ (4a) 6 × 10¹⁵ (4b)   4 × 10¹⁵ 3 × 10¹⁵(4d) embodiment (4c) Modified   8 × 10¹⁵ (5a) 6 × 10¹⁵ (5b)   4 × 10¹⁵ 3× 10¹⁵ (5d) example (5c) 5th   1 × 10¹⁶ (6a) 6 × 10¹⁵ (6b)   5 × 10¹⁵ 3× 10¹⁵ (6d) embodiment (6c)(1a) 4.5 × 10¹⁵ + 5 × 10¹⁴ × 6(2a) 5.5 × 10¹⁵ + 5 × 10¹⁴ × 4(3a) 5 × 10¹⁵ + 5 × 10¹⁴ × 8(4a) 5 × 10¹⁵ + 5 × 10¹⁴ × 6(5a) 6 × 10¹⁵ + 5 × 10¹⁴ × 4(6a) 6 × 10¹⁵ + 5 × 10¹⁴ × 8(1b) 4.5 × 10¹⁵ + 5 × 10¹⁴ × 3(2b) 5.5 × 10¹⁵ + 5 × 10¹⁴ × 1(3b) 5 × 10¹⁵ + 5 × 10¹⁴ × 2(4b) 5 × 10¹⁵ + 5 × 10¹⁴ × 2(5b) 6 × 10¹⁵(6b) 6 × 10¹⁵(1c) 2.25 × 10¹⁵ + 2.5 × 10¹⁴ × 6(2c) 2.75 × 10¹⁵ + 2.5 × 10¹⁴ × 4(3c) 2.5 × 10¹⁵ + 2.5 × 10¹⁴ × 8(4c) 2.5 × 10¹⁵ + 2.5 × 10¹⁴ × 6(5c) 3 × 10¹⁵ + 2.5 × 10¹⁴ × 4(6c) 3 × 10¹⁵ + 2.5 × 10¹⁴ × 8(1d) 2.25 × 10¹⁵ + 2.5 × 10¹⁴ × 3(1d) 2.75 × 10¹⁵ + 2.5 × 10¹⁴ × 1(1d) 2.5 × 10¹⁵ + 2.5 × 10¹⁴ × 2(1d) 2.5 × 10¹⁵ + 2.5 × 10¹⁴ × 2(1d) 3 × 10¹⁵(1d) 3 × 10¹⁵—Specific Alignment Conditions for Resist Mask and Gate ElectrodeSuitable for Tilt-angled Ion Implantation—

Next paragraphs will describe alignment rules for the resist mask forthe tilt-angled ion implantation, and alignment rules for the gateelectrode taking the tilt-angled ion implantation into account, whichare applicable to the fourth through ninth embodiments.

Fourth and Fifth Embodiments

FIG. 35 shows a method of determining an alignment rule of a resistmasks 31 through 34 with respect to the gate electrodes 6 a, 6 b (simplyreferred to as “gate electrode”, hereinafter), which is applicable tothe fourth and fifth embodiments. Rp1 represents the length of thesidewalls 9 a, 9 b (simply referred to as “sidewall” hereinafter)sufficient for shielding impurity implanted along direction inclined,and Rp2 represents the length of the resist mask sufficient forshielding impurity implanted along direction inclined.

First, L1′ is determined so that the projection range of the impurityimplanted along a direction inclined in the sidewall will be longer thanRp1 based on the shape of the over-etched sidewall. Next, L1″ isdetermined so that the projection range of the impurity implanted alonga direction inclined in the resist mask will be longer than Rp2. L1′ andL1″ are then compared, the shorter one of which is defined as L1, and arule for the distance between the gate electrode and resist mask can begiven as L1−ΔL, where ΔL is an alignment error between the gateelectrode and resist pattern.

FIGS. 36 and 37 show a method of determining an alignment rule for thecase with aligned gate electrodes in the fourth and fifth embodiments.

Rp3 herein represents the length of the gate electrode sufficient forshielding impurity implanted along direction inclined.

First, L2′ is determined so that the projection range of the impurityimplanted along a direction inclined in the over-etched sidewall will belonger than Rp1 based on the shape of the over-etched sidewall. Next,L2′″ is determined so as to allow the projection range of the impurityimplanted along a direction inclined in the gate electrode impurity willbe longer than Rp3. L2′ and L2′″ are then compared, and the shorter oneof which is defined as L2. Assuming now a minimum formable width of aresist pattern 111 as L3. If the distance between the adjacent gateelectrodes is longer than 2(L1−ΔL)+L3, the resist pattern 111 can beformed between the adjacent gate electrodes according to the rule shownin FIG. 37.

On the other hand, if the distance between the adjacent gate electrodesis shorter than 2(L1−ΔL)+L3 but longer than L2, it is necessary to fillthe space between the adjacent gate electrodes with a resist pattern 111having a width of L3. If the distance between the adjacent gateelectrodes is shorter than L2, there is no need to form the resistpattern 111 between the adjacent gate electrodes.

Sixth through Ninth Embodiments

FIG. 38 shows a method of determining an alignment rule of a resistmasks 35 through 38, 41 and 42 with respect to the gate electrode, whichis applicable to the sixth through ninth embodiments. Rp2 represents thelength of the resist mask sufficient for shielding impurity implantedalong direction inclined, and Rp3 represents the length of the gateelectrode sufficient for shielding impurity implanted along directioninclined.

First, L1″ is determined so that the projection range of the impurityimplanted along a direction inclined in the resist mask will be longerthan Rp2. Next, L1′″ is determined so that the projection range of theimpurity implanted along a direction inclined in the gate electrode willbe longer than Rp3. L1″ and L1′″ are then compared, the shorter one ofwhich is defined as L1, and a rule for the distance between the gateelectrode and resist mask can be given as L1−ΔL, where ΔL is analignment error between the ate electrode and resist pattern.

FIGS. 39 and 40 show a method of determining a rule for the case withaligned gate electrodes in the sixth through ninth embodiments. Rp3herein represents the length of the gate electrode sufficient forshielding impurity implanted along direction inclined.

First, L2 is determined so that the projection range of the impurityimplanted along a direction inclined in the gate electrode will belonger than Rp3. If the distance between the adjacent gate electrodes islonger than 2(L1−ΔL)+L3, the resist pattern 111 as a part of the resistmask can be formed between the adjacent gate electrodes according to therule shown in FIG. 40, where L3 is a minimum formable width of theresist pattern 111.

On the other hand, if the distance between the adjacent gate electrodesis shorter than 2(L1−ΔL)+L3 but longer than L2, it is necessary to fillthe space between the adjacent gate electrodes with a resist pattern 111having a width of L3. If the distance between the adjacent gateelectrodes is shorter than L2, there is no need to form the resistpattern 111 between the adjacent gate electrodes.

Other Embodiments

This embodiment materializes a CAD software for producing a resist maskaccording to the rule explained referring to FIGS. 35 to 40. This makesit possible to readily produce a reticle for forming the resist maskwhich can prevent the impurity introduced along a direction tilt-angledfrom getting into the source-and-drain region. This can be realized byrunning a program stored in an RAM or ROM of a computer. Also suchprogram and a computer-readable storage medium having recorded thereinsuch program also fall within a scope of the present invention.

More specifically, the program is provided to a computer while beingstored in a recording medium such as CD-ROM, or other varioustransmission media. The recording media, besides CD-ROM, capable ofstoring the program include flexible disk, hard disk, magnetic tape,magneto-optical disk and non-volatile memory card. On the other hand,the transmission media for the program include a communication medium(such as connected line such as using optical fiber, or radio line) in acomputer network system (e.g., LAN, WAN such as the Internet, radiocommunication network), whereby program information is transmitted asbeing modulated by a carrier wave.

The aforementioned program fall within a scope of the present inventionnot only for the case where the functions of the above-describedembodiments are materialized by the supplied program run on a computer,but also for the case where the functions of the above-describedembodiments are realized by the program in cooperation with an OS(operating system) run on the computer or with any other applicationsoftware, and for the case where the functions of the above-describedembodiments are realized by the whole or a part of the program executedon a function expansion board or function expansion unit of thecomputer.

For example, FIG. 41 shows a block diagram of an internal constitutionof a general personal user terminal device. In FIG. 41, referencenumeral 1200 denotes computer PC. The PC 1200 has a CPU 1201, which isdesigned to execute a device control software stored in a ROM 1202 or ahard disk (HD) 1211, or supplied from a flexible disk drive (FD) 1212,so as to totally control the individual devices connected to a systembus.

1-18. (canceled)
 19. A semiconductor device comprising: a gateelectrode; source-and-drain regions; sidewalls covering only the lowerportion of both side faces of said gate electrode; and a silicide filmformed on the exposed surface of said gate electrode, wherein said gateelectrode contains an impurity having a conductivity type same as thatof the impurity contained in said source-and-drain regions, and saidgate electrode has an impurity concentration larger than that of saidsource-and-drain regions.
 20. The semiconductor device according toclaim 19, wherein said silicide film is formed as being extended fromthe top surface to the upper portion of both side faces of said gateelectrode.
 21. The semiconductor device according to claim 19, whereinsaid sidewalls are composed only of an oxide film.
 22. A computerprogram product comprising a computer-readable program code means forallowing a computer to execute a procedure for automatically forming anopening in a resist which covers a semiconductor substrate used formasking thereof in a process of introducing an impurity into a gateelectrode along a direction tilt-angled to the surface of saidsemiconductor substrate, said opening being formed in a size whichensures protection of areas for forming source-and-drain regions on bothsides of said gate electrode from the tilt-angle introduction of theimpurity.
 23. A computer-readable recording medium having recordedtherein a program product, said program product comprising acomputer-readable program code means for allowing a computer to executea procedure for automatically forming an opening in a resist whichcovers a semiconductor substrate used for masking thereof in a processof introducing an impurity into a gate electrode along a directiontilt-angled to the surface of said semiconductor substrate, said openingbeing formed in a size which ensures protection of areas for formingsource-and-drain regions on both sides of said gate electrode from thetilt-angle introduction of the impurity.